Conventional delay models for circuits or gates use at most one supply voltage parameter and do not separately consider supply and ground voltage shifts at driving blocks, which can affect the signal swing at the gate input and therefore affect the delay of the driven gate. Such supply and ground voltage differences may occur due to power supply noise, e.g., static power supply noise due to IR drop and/or transient power supply noise due to varying power demand interactions with image/package RLC distribution network. They also may occur in the presence of voltage islands, as described further below.
Circuit delay generally depends on both the supply voltage of the cell and the signal swing of its input, which in turn depends upon the source cell supply and ground voltages. In conventional delay models the input swing is assumed to match the cell's own ground-to-Vdd, and explicit level shifters are required to transmit signals between cells with large supply voltage differences. However, these are special cells level shifter cells have delays characterized with respect to multiple supply voltages. Level shifters are required when transmitting signals from a low supply voltage source cell to a high supply voltage sink cell to fully turn off devices in sink gate and thereby reduce noise sensitivity and power consumption in the sink cell. But level shifters are required when transmitting signals from a high supply voltage cell to a low supply voltage cell only to be able to bound delays in early mode timing analysis, and waste time, area, and power, since the circuit would operate correctly without them.
Moreover, sensitivity of delay to voltage increases at lower supply voltages necessary for low power, and thus the error in delay estimation incurred when the effect of source cell supply voltage is ignored also increases.
The significance of such variations has been shown by R. Ahmadi et al., “Timing Analysis in Presence of Power Supply and Ground Voltage Variations,” ICCAD 2003, pp. 176-183, and S. Pant et al., “Vectorless Analysis of Supply Noise Induced Delay Variation,” ICCAD 2003, pp. 184-191. These papers propose extending the characterization space for the gate delay to include additional parameters for the driving block ground and supply voltage. However this approach has several drawbacks. First, it would require recharacterizing or establishing additional delay models for the circuit library, thereby increasing rule size, and could not be applied without cooperation from the library provider. Second, each additional characterization dimension added to a gate delay characterization process can significantly increase (at least double) the delay characterization cost, and this cost can already require weeks if not months of simulation time.
Moreover, a more detailed journal article: L. Chen et al., “Buffer Delay Change in the Presence of Power and Ground Noise,” IEEE Transactions on CAD, v. 11, n. 3, Jun. 2003, pp. 461-473, like the papers discussed above, proposes characterizing delay as a function of additional parameters, in this case representing the common mode and differential power supply noise on a cell.
With increasing use of voltage islands, it becomes more important to be able to accurately compute the delay of a driven gate whose supply and/or ground values differ from those of its driving gate. When the ground of a driven gate is significantly lower than that of its driving gate, a low signal will not completely turn off an NFET connected to ground in the driven gate. Similarly, when the supply voltage of a driven gate is significantly higher than that of its driving gate, a high signal will not completely turn off an PFET connected to the supply voltage in the driven gate. In either of these cases a level shifting circuit, whose delay is specially characterized as a function of two supply voltages, is required to prevent excessive current leakage. But in other cases (e.g., driving from a high voltage island to a low voltage island sharing a common ground) a level shifter is not electrically necessary. However some timing methodologies require level shifters in these cases as well because conventional timing analysis methods do not accurately model the delay variation caused by having a different supply voltage on the driving and driven gates, and may overestimate the early mode, or minimum cell delay, leading to invalid timing analysis of the design. These level shifters add area, power, and delay, and are thus undesirable.
While delay calculation language (DCL) provides for adjusting thresholds between cells, no specific formulas are described in the DCL specification, i.e., such adjustment is intended to be left to the rule developer. Moreover, this only addresses one aspect of delay from source/sink voltage differences.
Transistor-level timing analysis has been utilized, which performs circuit simulation during timing and is therefore able to directly model source/sink voltage differences. However this analysis is expensive and does not scale well to very large designs.
Thus, there is a need for a method which more accurately estimates the delay of a gate driven by a gate with different supply and/or ground voltages without requiring recharacterization of the gate delay library.